As a Junior Researcher in System Modeling, you will support the development and use of executable system-level models and virtual prototypes using either the MathWorks toolchain (MATLAB/Simulink/Simscape) or SystemC/TLM. You will help quantify PPA and related KPIs to guide architecture exploration and design decisions. This is a hands-on, learning-focused role with strong mentorship and collaboration with cross-functional teams.
Assist in building and extending system-level models in MATLAB/Simulink/Simscape/Stateflow or SystemC/TLM-2.0 for hardware–software co-simulation.
Set up and run experiments to measure PPA metrics: latency, throughput, utilization, energy/operation, average/peak power, memory footprint, and basic area proxies.
Implement and calibrate entry-level power models (e.g., activity/state-based, DVFS scaling, clock/power gating effects) using specifications, RTL activity, or measured data.
Contribute simple device/IP models, bus/interconnect behavior, and software workload integration within a virtual platform environment.
Build or integrate basic plant/physical models (e.g., power stages, sensors/actuators) to support end-to-end system validation when relevant.
Automate simulations, parameter sweeps, and regressions; generate plots, dashboards, and concise summary reports using MATLAB or Python.
Perform basic sensitivity analysis and design-space exploration; highlight trade-offs and propose next steps based on data.
Support correlation of model results with RTL simulation, emulation, or silicon measurements; document assumptions and confidence levels.
Maintain clear documentation of modeling methodology, interfaces, KPIs, and results; follow coding standards, reviews, and version control (Git).
Participate in literature reviews, internal seminars, and knowledge-sharing; contribute to invention disclosures or publications when appropriate.
Collaborate with senior researchers, system architects, firmware, and verification teams to reproduce issues and iterate model fidelity and runtime.
Skills & Eligibility
Bachelor’s or Master’s in Electrical/Electronics Engineering, Computer Engineering, or a related field.
Solid fundamentals in digital logic, computer architecture, and embedded systems; exposure to control systems or signal processing is a plus.
Familiarity with at least one modeling path:MathWorks: MATLAB, Simulink; exposure to Simscape/Stateflow is a plus.SystemC/TLM: basic C++ proficiency and understanding of TLM-2.0 (LT/AT) concepts is a plus.
MathWorks: MATLAB, Simulink; exposure to Simscape/Stateflow is a plus.
SystemC/TLM: basic C++ proficiency and understanding of TLM-2.0 (LT/AT) concepts is a plus.
Understanding of PPA basics:Performance: latency, throughput, utilization, bottlenecks, buffers/queues.Power: dynamic vs. leakage, DVFS, clock/power gating, energy/operation.Area: main contributors (logic vs. memory) and simple parametric estimates.Thermal: awareness of thermal constraints; basic RC intuition is a plus.